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Job Description
Senior Digital Design Engineer We’re looking for a Senior ASIC Digital Design EngineerExperience required RTL Design with system Verilog Linting checks with spyglass STA Synthesis Experience with formal verification would be a plus Key Qualifications BS/MS degree with a minimum of 8years of related experience.Proficient in scripting languages (Python, Tcl Perl, unix shell)Familiar with RTL best design practices with SystemVerilogFamiliar with implementation and verification front end flowsStrong communication skills #J-18808-Ljbffr