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Job Description
Seeking a seasoned ASIC Verification Engineer with 8+ years of experience in Verification working with Verilog and/or System Verilog to join a leading Semiconductor company in Dublin.
As a key member of the IP Development team, you will be responsible for developing System Verilog – UVM testbenches and solving complex problems related to test bench development.
Key responsibilities include:
- Developing System Verilog – UVM testbenches from scratch
- Solving complex problems related to test bench development
- Defining and writing functional coverage models
- Debugging failing test cases to root cause
- Participating in reviews to ensure test bench meets quality and is complete
- Contributing to verification perspective in Design and Concept meetings
- Ensuring test bench meets sign-off targets, including coverage, functional safety and test bench qualification
- Proactively helping increase efficiency of verification activities and mitigating risks early
- Contributing to enhancing Verification strategy and architecture of IP testbenches
Key skills required:
- At least 8 years of experience in Verification working with Verilog and/or System Verilog
- 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform
- Ability to understand complex design specifications, derive features, and test bench architectures from concept
- Familiarity with CAD/EDA tools for Design and Simulation
- Working knowledge in scripting languages for verification environments (Python, Perl, TCL)
- Strong background in Digital Logic Design and Verification
The company offers a competitive compensation package, including a generous base and bonus scheme, as well as ongoing training and support, flexible working conditions, sabbaticals, health care, private insurance offers, and pension plans.
EU Nationals can work without sponsorship, and relocation is a must for this role.