Job Description
Job Summary: Participate in the development of a new decoder block for high performance reception by translating signal processing algorithms into fully synthesizable RTL code.
Key Responsibilities:
Translate signal processing algorithms into fully synthesizable RTL code
Propose a micro-architecture, Verilog coding, simulation, and verification of a new block that reduces die size by 2-4
Integrate the new block into different Wi-Fi IP versions and support the UVM team for debugging
Collaborate with signal processing and HW engineers
Requirements:
Engineering degree in Computer Sciences
8+ years of experience in digital design
Ability to follow a design flow (RTL, testbench, code coverage, synthesis, formal verification, gate level simulation)
Highly experienced in Verilog
Strong background in communication theory and digital signal processing, OFDM and MIMO technologies a high plus
Familiar with Matlab
Strong written communication skills in Functional, Design, and Test Plan Documentation
Excellent communications and interpersonal skills, English required