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Job Description
Design high-speed memory interface analog components for state-of-the-art DDR memory interface PHYs in leading-edge technology nodes.
Responsibilities include designing memory interface products at data rates up to 36 Gbps, collaborating with global teams, and mentoring junior design engineers.
Key requirements include a BEng, MEng qualification, minimum 4 years of CMOS design experience, and proficiency in CAD tools.
Design experience in CMOS SERDES, DDR or high-speed I/O IC design, and good understanding of jitter and signal equalization techniques are required.