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Job Description
Principal Design Engineer (DDR/Memory) responsible for designing state-of-the-art DDR memory controllers for various applications, including Datacenter, Edge computing, Automotive, and AI.
The Cadence Silicon Solutions Group develops leading edge Intellectual Property (IP) for High-Tech Markets.
Job Responsibilities:
- Architect solutions for the latest DDR controller features and customer requirements.
- Design RTL in a highly configurable and automated environment.
- Work in small project teams.
- Collaborate with Design Verification, Support, Delivery, Application Engineers, and PHY design team.
- Utilize Cadence's Design Automation flow and IP development tools.
- Develop high-speed circuits and low-power features.
- Improve quality and efficiency, and refine development process for greater productivity of the team.
Job Qualifications:
- 10+ years' experience in microelectronics/EDA industry.
- Experience of Verilog RTL Design essential.
- Experience of Metric Driven Verification (MDV) essential.
- Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential.
- Experience of SoC Architecture and Development essential.
- Experience of Technical Team leadership essential.
- Excellent oral and written English essential.
Additional Skills/Preferences:
- Experience of AMBA protocols such as CHI, AXI, AHB & APB preferred.
- Experience of System Verilog for design preferred.
- Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.