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Job Description
Highly experienced Principal Design Engineer with 10+ years in microelectronics/EDA industry sought to lead development of leading edge DDR memory controllers in Cadence Silicon Solutions Group (SSG) design team. Key responsibilities include architecting solutions for latest DDR controller features, designing RTL in configurable environment, working in small project teams and utilizing Cadence's Design Automation flow and IP development tools. Essential qualifications include degree in Electrical/Electronic Engineering or related discipline, experience in Verilog RTL Design, Metric Driven Verification and Front-end design tools. Additional skills in AMBA protocols, SystemVerilog and Quality processes are preferred.