Job Description
Principal Digital Design Engineer Location: Cork Reports to: Design Engineering Director Job Overview: The Cadence Silicon Solutions Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence IP Vision is to deliver industry leading IP solutions to enable our customers to be successful across these fast-moving application spaces. The Principal Design Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US, and India. Job Responsibilities: Technical leadership of complex IP such as Ethernet, Storage, PCIe/CXL, MIPI - Visual preference but not essential. Develop comprehensive verification plans and testbenches to rigorously validate the functionality and performance. Conduct power and timing analysis to optimize the chip's power consumption, performance, and timing closure, collaborating closely with physical design and implementation teams as needed. Hands-on leadership of RTL, Testbenches & FPGA Platforms development. Planning of activities and milestones for the Digital Controller Development teams. Leadership of cross-functional technical meetings with Analog & Software counterparts. Support customer pre-sales and post-sales meetings. Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001. Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI-SIG, JEDEC, MIPI. Represent Cadence by presenting at Industry Conferences such as IEEE, DAC, MIPI Alliance. Job Qualifications: Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. 10+ years’ experience in microelectronics/EDA industry. Experience of Verilog RTL Design essential. Experience of Metric Driven Verification (MDV) essential. Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential. Experience of SoC Architecture and Development essential. Experience of Technical Team leadership essential. Excellent oral and written English essential. Self-motivated with excellent planning, interpersonal, and communication skills. Additional Skills/Preferences: Experience of AMBA protocols such as AXI, AHB & APB preferred. Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred. Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred. Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. We’re doing work that matters. Help us solve what others can’t. #J-18808-Ljbffr