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Job Description
Principal Digital Design Verification Engineer, Cork City, Ireland
Our client, a leading Multinational Semiconductor EDA provider, requires a Principal Digital Design Verification Engineer for a role based in Cork City, Ireland.
A leading Multinational Semiconductor EDA provider seeks a Principal Digital Design Verification Engineer to join their team in Cork City, Ireland.
The successful candidate will be responsible for the Design Verification of Intellectual Property (IP) for a variety of High-Tech Markets.
This is an opportunity to join a development team designing state-of-the-art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI.
The Principal Digital Design Verification Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, the US, and India.
- Responsibilities:
- Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage.
- Development of UVM-SV Scoreboards for self-checking regressions.
- Development of Functional Coverage as part of Metric Driven Verification Environments.
- Development of System Verilog Assertions for use in Formal and Simulation Environments.
- Definition and Management of Verification Plans (v Plans) using Cadence v Manager tools.
- Creation and Management of Automated Regression Environments, e.g. Jenkins.
- Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
- Closed Collaboration with Design Engineers to debug complex test scenarios.
- Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods.
- Work across disciplines with Design, Support, Delivery, Application Engineers, PHY team, etc.
Qualifications:
Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
10-15 years' experience in microelectronics/EDA industry.
Experience of System Verilog Constrained Random Verification essential.
Experience of Metric Driven Verification (MDV) essential.
Excellent oral and written English essential.
Self-motivated with excellent planning, interpersonal, and communication skills.
Additional Skills/Preferences:
Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred.
Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
AXI and/or CHI-E experience is highly desirable.