Job Description
Principal Verification Engineer Apply locations CORK 01 Time type: Full time Posted on: Posted 14 Days Ago Job requisition id: R47422 At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. Job Title: Principal Digital Verification Engineer Location: Cork Reports to: Design Engineering Director Job Overview: The Cadence Silicon Solutions Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence IP Vision is to deliver industry leading IP solutions to enable our customers to be successful across these fast-moving application spaces. The Principal Digital Verification Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US and India. Job Responsibilities: Architecture of verification environments for existing complex protocols IP such as CXL, CXS, PCIe and the cutting edge of the latest UCIe technologies. Lead development of Formal First methodologies and drive adoption/implementation using industry leading tools such as JasperGold. Development of SystemVerilog assertions, assumptions and covers for use in Formal and Simulation Environments. Experience creating Formal properties from Protocol specifications. Close collaboration with Design Engineers to debug complex test scenarios. Development of UVM-SV Scoreboards for self-checking regressions. Development of Functional Coverage as part of Metric Driven Verification Environments. Definition and Management of Verification Plans (vPlans) using Cadence vManager tools. Creation and Management of Automated Regression Environments, e.g. Jenkins. Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001. Job Qualifications: Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. 10+ years’ experience in microelectronics/EDA industry. Experience of Verilog RTL Design essential. Experience of Metric Driven Verification (MDV) an advantage. Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis an advantage. Experience of SoC Architecture and Development an advantage. Experience of Technical Team leadership an advantage. Additional Skills/Preferences: Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred. Experience of AMBA protocols such as AXI, AHB & APB preferred. Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel: < 5% We’re doing work that matters. Help us solve what others can’t. #J-18808-Ljbffr