Job Description
We are seeking an ambitious analog designer to work on leading-edge Wireline technology at high data rates (112 Gbps+) and on small technology nodes (e.g. 3nm) for the Cadence Serdes PHY team in Cork, Ireland. The successful candidate will take a technical leadership role on the verification team and be responsible for the verification of High Speed SERDES products, specification, design and verification of High Speed PHY IP, and implementation of customer delivery and support. The ideal candidate will have a strong background in CMOS SERDES or high-speed I/O IC design and development, experience with digital design and verification tools, and excellent problem-solving skills. Prior experience with post-silicon validation and customer IP deployment is an added advantage. The role requires excellent communication and stakeholder management skills and the ability to work cooperatively in a team environment. The successful candidate will participate in technical leadership of the team and work with global teams in different time zones. We are looking for a candidate with a BEng, MEng, or Ph.D. in a relevant field and at least 7 years of experience in CMOS SERDES or high-speed I/O IC design and development. The successful candidate will be part of a dynamic team that works on innovative products and technologies and will have the opportunity to make a significant impact on the company's success.