Job Description
Principal Verification Engineer (SERDES) role at Cadence, responsible for verification of high-speed SERDES products, specification, design, and verification of high-speed PHY IP, and technical leadership of the verification team.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.
The Cadence Serdes PHY team is seeking ambitious analog designers who wish to work on the leading edge of Wireline technology at the highest data rates (112 Gbps+) and on the smallest technology nodes (e.g. 3nm).
Key Responsibilities:
- Verification of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm Fin FET CMOS).
- Specification, Design and Verification of High Speed PHY IP based on communication protocols (PCIe, Ethernet).
- Verification from initial concept/specification through final verification of conformance to customer specifications using Coverage metric.
- Implementation, Tracking and Closure.
- Prototyping, Emulation, Customer delivery and support.
Requirements:
- BEng, MEng, Ph D or equivalent.
- Candidate's background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development.
- Working knowledge of a set of common SERDES standards.
- Wide experience with digital design and verification tools; RTL design using Verilog & verification with System Verilog and UVM.
- Experience of Assertion Based Formal Verification essential.
- Experience of Front-end design tools covering LINT, Synthesis & CDC Analysis.
Additional Skills/Preferences:
- Prior experience with post Silicon validation & customer IP deployment of one or more Serial IO IPs/ complex Memory Interface IPs is an added advantage.
- Knowledge of PCIe, CXL protocols preferred.