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Job Description
Job Summary:
We are seeking an experienced ASIC Verification Engineer to join our dynamic team.
As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs.
If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.
Responsibilities:
Verification Planning and Execution: Develop and execute comprehensive verification plans.
Close verification with coverage closure, ensuring high-quality results.
Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.
Testbench Development:
Create and enhance testbenches using System Verilog (OVM/UVM) or other standard testbench languages.
Implement reusable Verification IP (VIP) components.
Collaborate with third-party VIP providers.
Develop vertically and horizontally reusable testbenches.
Methodology and Flows:
Demonstrate a solid understanding of ASIC design and verification methodologies.
Apply object-oriented programming principles effectively.
Implement constraint random verification methodology.
Technical Skills:
Proficiency in System Verilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI, SV/DPI).
Familiarity with industry standards (e.g., I2 C/SPI/AHB).
Gate level simulation.
Experience with low-power verification using UPF (Unified Power Format) is a plus.
Knowledge of formal verification techniques is advantageous.
Collaboration and Communication:
Work effectively with internal teams and external customers.
Strong written and verbal communication skills.
Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.
Requirements:
Qualifications: Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or related fields.
Experience:
Graduation: 8-12 years,
Post Graduation: 7-12 years of experience.
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