Senior Engineer, Design Verification Engineering - Analog Devices
  • Munster, Munster, Ireland
  • via BeBee.com
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Job Description

Analog Devices, Inc. is a global semiconductor leader bridging the physical and digital worlds to enable breakthroughs at the Intelligent Edge.

The company combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.

Senior Analog Design Verification Engineer is responsible for ensuring a circuit design performs according to the product's technical specifications over the required conditions.

  • Transistor-level circuit simulations over corner including PVT, loading conditions, and Monte Carlo
  • Understanding of semiconductor device level operation & physics
  • Behavioral modelling to enable comprehensive, top-down, metric-driven verification of new analog designs
  • Working together with a broad team of engineers distributed across the globe
  • Leveraging existing design verification IP to enable full coverage of new designs
  • Supporting other job functions such as board design, lab evaluation and test to ensure successful delivery meeting key requirements

Requirements:

  • Excellent knowledge of analog and mixed-signal circuit design, tools, and flows
  • Experience with scripting languages such as Python, Tcl, or Perl
  • Experience in stability of feedback systems and compensation techniques
  • Experience in bipolar circuit design and/or high-speed amplifiers is a plus
  • Knowledge of precision metrics such as mismatch, noise & linearity is a plus
  • Design experience in amplifiers circuits, DACs, ADCs, bandgaps, or bias circuits is a plus

Minimum Qualifications:

  • MS / Ph D degree in EE or ECE with focus on analog/mixed signal design with 3+ years of relevant industry experience

Preferred Skills & Experience:

  • Knowledge of standard verification flows including UVM, testbench automation, coverage-based metrics is a plus
  • Knowledge of verification languages like Verilog/Verilog A, System Verilog, Verilog-AMS, System-C, etc. is a plus
  • Experience with C++ and Matlab
  • Strong presentation and technical documentation skills
  • Strong analytical and problem-solving skills with attention to detail
  • Self-motivated, thorough, autonomous, and driven to continually improve

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