Job Description
Company: QT Technologies Ireland Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: About The Role Qualcomm offers flexible work options tailored to our employee’s needs. These include a combination of work from home and working in our brand new, state of the art office in Penrose Dock, Cork. Well-being and life balance are fundamental to Qualcomm as an employer. We recognise and understand that employees have missed spending quality time with loved ones and extended family. As such, Cork Qualcomm policy allows our employees to blend short-term remote working with annual leave. Job description: Applies knowledge and experience to architect, design, implement, the testbench to verify the structure and performance computer vision IPs Creates and maintains verification test benches and environments in System Verilog/UVM Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams to define and develop test methodology and content Participate in micro-architecture reviews Collect, organize and execute various forms of system level test content including directed testcases, standards compliance test suites, and system level scenarios Build automation for continue integration and testing based on latest IP Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues Works with team members to understand and align on narrow scope of feature development and meet targets. Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor. Experience in system or sub-system level verification Concurrency, Preemption, Stress testing frameworks Testbench Architecture and Implementation Scripting and automation skills (Python, Make, Airflow etc) Embedded FW Development and Debugging Benchmarking and Performance Analysis Formal verification experience is a plus Experience with emulation/prototyping/hybrid build and execution flows (Veloce, Palladium, Zebu, Protium, HAPS, qemu) is a plus Development of synthesizable transactors, monitors, scoreboards for emulation platforms would be a plus Qualifications: Minimum 3 years of DV experience using uvm/assertion-based verification technologies Experience in verifying complex SOC or SOC subsystems Experience with caches and DDR memory protocol verification Experience with using memory verification VIP's Exposure with multiple successful tapeouts from conception to post silicon debug Exposure to Formal verification Experience with Power aware simulations. Experience with perf and power verification. Experience with Gate level Simulations Comprehensive knowledge of interconnect protocols such as APB, AHB, AXI, ACE, ACE-Lite, and NoC concepts. Expertise in diverse integration tasks, including VIP Configuration, Register Model, and Design Debug Features. Skill proficiency: UVM, system verilog, assertion, C++, python, Power Aware simulations, Gate level Simulations Where you will be working Cork has a proud reputation as Ireland's second largest economic engine and is now one of the Top 20 location choices in Europe with 39,000 people being employed by over 170 overseas companies. Equal OpportunitiesWe are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any protected classification. What's on Offer Apart from working in an open, relaxed and collaborative space, you will enjoy: Salary, stock and performance related bonus Maternity/Paternity Leave Employee stock purchase scheme Matching pension scheme Education Assistance Relocation and immigration support (if needed) Life, Medical, Income and Travel Insurance Subsidised memberships for physical and mental well-being Bicycle purchase scheme Employee run clubs, including, running, football, chess, badminton + many more Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. *References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies. #J-18808-Ljbffr