-
Job Description
Job Title: ASIC Design Verification Engineer
Summary: Design and verify complex computer vision IPs, create and maintain verification test benches, and collaborate with cross-functional teams to develop test methodology and content.
Company: Qualcomm Technologies Ireland Limited
Job Area: Engineering Group, Engineering Group ASICS Engineering
Location: Cork, Ireland
Job Description:
- Architect, design, implement, and testbench to verify the structure and performance of computer vision IPs
- Create and maintain verification test benches and environments in System Verilog/UVM
- Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions
- Collaborate with Architecture, Software, Firmware, Design, Modeling, Emulation, and Post-silicon validation teams to define and develop test methodology and content
- Participate in micro-architecture reviews
- Collect, organize, and execute various forms of system level test content, including directed testcases, standards compliance test suites, and system level scenarios
- Build automation for continuous integration and testing based on latest IP
- Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues
- Work with team members to understand and align on narrow scope of feature development and meet targets
- Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor
Qualifications:
- Minimum 3 years of DV experience using uvm/assertion-based verification technologies
- Experience in verifying complex SOC or SOC subsystems
- Experience with caches and DDR memory protocol verification
- Experience with using memory verification VIP's
- Exposure with multiple successful tapeouts from conception to post silicon debug
- Exposure to Formal verification
- Experience with Power aware simulations
- Experience with perf and power verification
- Experience with Gate level Simulations
- Comprehensive knowledge of interconnect protocols such as APB, AHB, AXI, ACE, ACE-Lite, and No C concepts
- Expertise in diverse integration tasks, including VIP Configuration, Register Model, and Design Debug Features
Skills:
- UVM
- System Verilog
- Assertion
- C++
- Python
- Power Aware simulations
- Gate level Simulations
What's on Offer:
- Salary, stock, and performance-related bonus
- Maternity/Paternity Leave
- Employee stock purchase scheme
- Matching pension scheme
- Education Assistance
- Relocation and immigration support (if needed)
- Life, Medical, Income, and Travel Insurance
- Subsidized memberships for physical and mental well-being
- Bicycle purchase scheme
- Employee-run clubs, including running, football, chess, badminton, and many more