Job Description
**Job Summary**
Architect and design verification testbenches and environments in System Verilog/UVM, create and leverage advanced testing frameworks, and collaborate with cross-functional teams to define and develop test methodology and content.
**About the Role**
QT Technologies Ireland Limited is seeking a Verification Engineer to join their Engineering Group, ASICS Engineering team. The ideal candidate will have a strong background in system or sub-system level verification, with experience in using uvm/assertion-based verification technologies and verifying complex SOC or SOC subsystems.
**Key Responsibilities**
- Architect and design verification testbenches and environments in System Verilog/UVM
- Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions
- Collaborate with Architecture, Software, Firmware, Design, Modeling, Emulation, and Post-silicon Validation teams to define and develop test methodology and content
- Participate in micro-architecture reviews
- Collect, organize, and execute various forms of system-level test content, including directed testcases, standards compliance test suites, and system-level scenarios
- Build automation for continuous integration and testing based on latest IP
- Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues
- Work with team members to understand and align on narrow scope of feature development and meet targets
- Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor
**Qualifications**
- Minimum 3 years of DV experience using uvm/assertion-based verification technologies
- Experience in verifying complex SOC or SOC subsystems
- Experience with caches and DDR memory protocol verification
- Experience with using memory verification VIP's
- Exposure with multiple successful tapeouts from conception to post-silicon debug
- Exposure to Formal verification
- Experience with Power aware simulations
- Experience with perf and power verification
- Experience with Gate level Simulations
- Comprehensive knowledge of interconnect protocols such as APB, AHB, AXI, ACE, ACE-Lite, and No C concepts
- Expertise in diverse integration tasks, including VIP Configuration, Register Model, and Design Debug Features
**Skills**
- UVM
- System Verilog
- Assertion
- C++
- Python
- Power Aware simulations
- Gate level Simulations
**What's on Offer**
QT Technologies Ireland Limited offers a competitive salary, stock and performance-related bonus, maternity/paternity leave, employee stock purchase scheme, matching pension scheme, education assistance, relocation and immigration support, life, medical, income, and travel insurance, subsidized memberships for physical and mental well-being, bicycle purchase scheme, and employee-run clubs.