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Job Description
Job Title: Verification Engineer
Company: [Company Name]
As a Verification Engineer, you will be responsible for implementing verification for block level, subsystem, and SoC level designs using advanced verification methodologies to meet quality and schedule goals. You will work with system architects and RTL designers to develop verification requirements and test plans based on specifications.
Key responsibilities include:
- Implementing verification for block level, subsystem, and SoC level designs
- Working with system architects and RTL designers to develop verification requirements and test plans
- Analyzing and debugging simulation failures
- Creating, tracking, and closing bugs in a bug tracking tool
- Analyzing code coverage and functional coverage reports
- Regression analysis
- Developing, maintaining, and publishing verification specifications
- Gate level simulations
Requirements include:
- BSEE/BSc (MEng preferred) as well as at least 9 years relevant work experience
- Fluent in System Verilog, UVM, and SVA
- Excellent debugging and problem-solving skills
- Familiarity with Metric Driven Verification methodology
- Experience in writing test plans and creating directed and random test cases
- Scripting skills in Python, Perl, shell, etc.
- Working knowledge of Linux operating system
- Embedded C experience considered an advantage
- Experience with Synopsys tool suite an advantage
- Preferably knowledge of AMBA and wired/wireless protocols
- Excellent written and oral communication skills
This role offers a challenging opportunity to work on complex verification projects and develop your skills in a dynamic environment.