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Job Description
Staff Level Digital Design Engineer
Transform next-generation computing experiences with innovative digital designs.
The AMD Ser Des team in Ireland is seeking a Staff level digital design engineer to lead the development of digital designs for complex mixed-signal ICs in the latest CMOS Fin FET processes.
This role involves the RTL design and implementation of complex clock and data recovery algorithms, adaptive digitally assisted control loops, and the development of advanced DSP designs to achieve power efficient channel equalization solutions.
Responsibilities:
- RTL implementation of algorithms for clock and data recovery, adaptive digital control, and DSP
- Communication with the architecture team to understand proposed algorithms and provide feedback regarding design implementation
- Digital design verification to ensure basic design functionality prior to hand-off of the design to verification team
- Design verification using standard industry tools for HDL checking
- Support of the verification team in the debug of identified issues
- Assist with silicon bring up and debug
- Creation of clear design specifications and implementation documentation
- Mentoring of junior team members
Requirements:
- Extensive experience in RTL design methodologies, specification development, and design implementation
- Familiarity with RTL design using a HDL such as Verilog or VHDL, Verilog being a preference
- Experience in modern digital ASIC methodologies including verification, STA, and signal integrity, DFT, synthesis, physical implementation
- "Tape-out" experience in advanced foundry process technologies
- Experience in silicon debug, verification, and characterization
- Excellent written and oral communication skills
- Good interpersonal/teamwork skills
Credentials:
- Bachelors Degree or Masters Degree in Electrical Engineering