Staff Senior Gpu Power Design Verification Engineer Job In Cork

staff-senior gpu power design verification engineer - Software Placements
  • Cork, Munster, Ireland
  • via BeBee.com
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Job Description

Senior GPU Power Verification Engineer

A leading Multinational Semiconductor Telecom Company is seeking a highly skilled Senior GPU Power Verification Engineer to join their team in Cork City, Ireland.

Key Responsibilities:

  • Collaborate with the Architecture and Design team to develop verification plans and test plan documents for low power design features.
  • Create verification components and testbenches for low power verification, integrate third-party VIPs/UVCs as required, and design a constraint random verification environment using System Verilog and UVM.
  • Perform Power Aware Verification in a random verification environment with embedded firmware running on the design.
  • Regress and close the required Low Power coverage metrics to ensure high-quality design.
  • Create portable test setups and verification components that can be reused across simulation and emulation platforms.
  • Perform failure debug involving hardware-software co-debug.
  • Work with tool vendors to improve the verification flows.
  • System level RTL simulation and design verification.
  • Support SoC DV for integration verification, chip bring-up, and post-silicon debug.

Requirements:

  • Bachelor's degree in Science, Engineering, or a closely related field.
  • 3+ years of hands-on experience in System Verilog, OVM/UVM based constrained random verification.
  • 3+ years in Design validation/Post-Silicon debug.
  • 3+ years of hands-on experience in developing verification components/UVCs and testbenches for RTL verification.
  • 3+ years of hands-on testbench bring-up, integrating third-party VIPs, digital design, verification, debugging, and waveform debug.
  • 2+ years of experience in UPF based Power Aware verification.
  • 2+ years of experience in Functional coverage model development and/or code coverage closure.
  • Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells, and state retention cells.

Desirable Skills:

  • MS degree in Electrical Engineering or equivalent; 8 years of practical experience.
  • Experience with Synopsys NLP (native Low Power) tool.
  • Working knowledge of GLS, PAGLS, and scripting languages such as Perl and Python.
  • Power Aware Emulation verification experience.
  • Hardware/Software Co-verification.
  • Experience with Low Power coverage metrics collection and coverage closure.
  • Knowledge of GPU/CPU/DDR/Bus.
  • Scripting skills using Python.
  • Formal verification experience (AND/OR) Low Power Formal Verification experience.

Working Model:

The company offers a hybrid working model of 3 days onsite and 2 days from home, prioritizing well-being and life balance.

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